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Additional info for ACM transactions on design automation of electronic systems (April)
For instance, Figure 1 shows the dynamic energy consumption breakdown in the storage hierarchy for the different storage components (TLBs, L1 and L2 caches, and off-chip DRAM) of a fourissue superscalar machine in the execution of six Spec2000 applications for a virtually indexed, physically tagged L1 addressing strategy. 3% of the energy in the memory hierarchy is consumed by the instruction TLB (iTLB) alone, which motivates the research presented in this article. The detailed discussion of our experimental setting and benchmarks will be given later in the article.
However, there is one specific component, namely, the Translation Look-aside Buffer (TLB), which has not drawn very much attention from the architectural/software angle for power optimization. In fact, this component is much more frequently accessed than DRAMs and many other components. An instruction fetch and data reference go through address translation via the TLB which is a cache of recent virtual-to-physical address translations. Even though this unit is typically kept small (to keep access times low), its associativity is usually high to keep miss rates low.
Such an ability can be used in a system that has a virtually indexed, physically tagged (VI-PT) iL1 cache, to lower iTLB power considerably. It can even lower iTLB power in a system with a virtually indexed, virtually tagged (VI-VT) iL1 cache by reducing lookups upon cache misses. Further, it can save cycles expended in iTLB lookups upon an iL1 miss for a VI-VT iL1 cache where the iTLB is in the critical path. Finally, if we are able to successfully provide translations in most cases, then we may want to even reconsider incorporating physically indexed, physically tagged (PI-PT) caches, which are largely ignored today because of translation getting in the critical path.